The present invention relates to electrically erasable programmable read-only memories (EEPROMs). In particular, it relates to circuits used to provide the voltage levels necessary to program EEPROMs.
The circuits used to provide the necessary voltage signal to program an EEPROM are called charge pumps. Such circuits are known.
A known charge pump 10 is shown in FIG. 1. The purpose of the circuit is to pass whatever voltage appears on external pin V.sub.ppin to V.sub.ppl, an internal node which is coupled to the memory cell being programmed. Ideally, there should be no voltage loss between V.sub.ppin and V.sub.ppl.
When the EEPROM is being programmed, STR goes low. The gates of transistors 11, 13 and 33 all receive this signal, turning the transistors off. Simultaneously, STR is applied to inverter 25, the resultant signal being applied to the gate of transistor 27. Transistor 27 turns on, applying a voltage of V.sub.cc -V.sub.t (V.sub.t is the voltage drop across a given transistor) to node 4.
The clock signal CLK now goes to a high voltage level. Assuming that the binary logic signals correspond to voltage levels of 0 volts for a logic 0, and 5 volts for a binary logic 1, node 4 now reaches approximately V.sub.cc -V.sub.t +V.sub.clk * X volts, where V.sub.clk is the clock amplitude swing and X is the capacitive divider ratio calculated as X=C.sub.D /C.sub.D +C.sub.S, where C.sub.D is the value of the pump capacitor(s) 21 and 23 and C.sub.S is the total junction capacitance on node 4, or roughly 9 volts, assuming V.sub.cc is 5 volts. As CLK is high, CLK is low. At this point, transistors 17, 19 and 29 are all on, as their gates receive a high voltage from node 4. As transistor 15's gate and drain are coupled to CLK, transistor 15 turns off. With transistor 17 conducting, node 6 climbs in voltage to V.sub.4 -V.sub.T, also charging capacitor 23. Node 6 will be limited to some fraction of V.sub.ppin, about 7-8 volts. Node 8 rises to V.sub.4 -V.sub.T where V.sub.4 is the voltage on node 4.
When CLK goes low and CLK goes high, transistor 15 turns on, the voltage on node 6 rises, and the voltage on node 4 begins to drop. However, the charge on capacitor 21 is supported by the current through transistor 15 as the voltage on node 6 rises due to CLK going high, and the voltage on node 4 only drops to about 12 volts. When the CLK and CLK signals again reverse themselves, the voltage on node 4 climbs again. As transistor 19 turns on again, the voltage on node 8 also climbs.
After about a microsecond, the circuit stabilizes with node 4 varying in voltage between 15 and 17 volts. Ideally, the voltage on node 4 coupled to the gates of transistors 29 and 19 should pass the V.sub.ppin voltage from node 2 to node 12.
The type of charge pump just described has several deficiencies. Transistors 11, 13 and 33 each have their gates grounded during programming. This limits the total voltage which can be applied to their drain without causing reverse breakdown of the transistor. Additionally, even if breakdown does not occur, leakage currents to ground can result, causing a loss of voltage to V.sub.pp1. As shown in FIG. 1, a maximum of roughly 16.5 volts can be applied to the drain of transistors 11 and 13 before the breakdown occurs. In turn, this requirement limits the maximum voltage that can be applied to the gate of transistor 29.
Node 4, after the circuit reaches equilibrium, alternates between 15 and 17 volts, establishing an A.C. voltage. This A.C. voltage is used to pass the D.C. voltage on node 2 to V.sub.ppl. This results in some A.C. coupling between node 4 and node 8 and node 4 and node 12 as V.sub.ppl approaches V.sub.ppin. The coupling again reduces the amount of charge that can be passed to V.sub.ppl.
The charge pump also uses two separate clock signals, CLK and CLK. Any time the two clocks become skewed with regards to one another, the efficiency of the charge pump decreases, as node 4 discharges to a lower level than optimum.
A charge pump without these noted deficiencies is clearly desirable.